Publication
IEEE T-ED
Paper

Source-Drain Contact Resistance in CMOS with Self-Aligned TiSi2

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Abstract

The contact resistance between TiSi2 and n+-p+ source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmissionline model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10-7 and 1 × 10 -6 Ω cm2 can be obtained for 0.5-0.20-μm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 10200/cm3. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi2-n+ and TiSi2-p+ interfaces. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.

Date

01 Jan 1987

Publication

IEEE T-ED