Image of a wafer

Silicon Bridge Chiplet Integration

Developing a new chiplet integration technology using silicon bridge for advanced semiconductor packaging.


As the benefits of transistor scaling diminish, heterogeneously integrated multi-chip packages are required to increase bandwidth and reduce latency of data transfer. Such packages especially enable AI workloads that require high-speed communication with low power dissipation per communication bit. Examples of such packages include silicon-interposers, high-density laminates, silicon-bridges, fan-out packages, and 3D. In a typical multi-flip-chip semiconductor package for server applications, the semiconductor chips are attached to an organic laminate substrate with over ten thousands of solder interconnects. The interconnects are encapsulated with a filled epoxy underfill material to reduce stress on the chip BEOL and interconnects. A thermal interface material resides in the gap between the chip and a heat spreader lid, which in turn is adhesively attached around the top of the laminate substrate.

State-of-the-art interconnect pitch on package substrates for processor chips is 130-150 µm. Communication between the chips takes place through the laminate substrate where the metal line widths and spacings are ~15-20 µm and the length of the wires for the interconnection is a few millimeters. With the advent of finer pitches such as 55 µm in high-bandwidth memory chips (HBM), alternate packaging schemes such as high-density laminates and silicon-interposer packages are being developed.

In a silicon-interposer package, the chips are mounted on a thinned silicon-interposer substrate, which is mounted on a laminate substrate. Signal communication between the chips occurs directly through wiring layers within the silicon-interposer, and power is delivered to the chips by through-silicon-vias (TSVs).

High-density laminates and fan-out packages require large-area and fine-pitch organic wiring layers (RDL: re-distribution layer). In a fan-out package, highly filled molding compound material is used to enable wafer-level processing for the warpage-sensitive fine-pitch RDL layers and to mitigate CPI (chip-package interaction) stress.

Since the silicon-interposers span the entire surface of multiple chips, stitching across multiple reticle fields is required as the requirement to integrate many chips on the same interposer increases. As the interposer size increases, the number of interposers available from a single wafer decreases. The cost of a silicon interposer packages can be significantly higher than that of flip chip laminate packages due to the complexity of wafer handling. Fan-out packages also have the same cost concern caused by the wafer-level packaging processes.

To circumvent some of the issues with silicon-interposer and RDL-type packages, we introduce a new interconnect technology, the DBHi silicon-bridge package. This enables use of standard pitch laminate substrates and realizes simpler and lower cost bond and assembly process without wafer molding and RDL process.

Key advantages of the silicon bridge packages are as follows.

  1. BEOL-level fine-pitch interconnect on silicon bridge enabling high bandwidth interconnect
  2. Matching chip and bridge CTE enabling fine pitch interconnect joints (~30 µm-pitch)
  3. Low BoM cost (use of standard-pitch substrate, but not required large silicon interposer, fine-pitch RDL, fine pitch or bridge-embedded substrate)
  4. Good reliability
Cross section image of silicon bridge structureCross section image of a silicon bridge structure.Illustration of a direct-bonded heterogeneous integration (DBHi) silicon bridge package.Illustration of a direct-bonded heterogeneous integration (DBHi) silicon bridge package.



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Semiconductor fabrication & packaging

We’re developing new materials for both the smallest length scale (<20nm) and largest length scale (>20mm) of semiconductor fabrication.
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The American Semiconductor Innovation Coalition

IBM is a founding member of ASIC, a diverse group united to advocate for U.S. semiconductor leadership.