The recently introduced Direct Bonded Heterogeneous Integration (DBHi) Si bridge technology consists of chips directly connected by a bridge chip though Cu pillars, enabling high speed and high band-width communication between CPUs, GPUs and memory chips. The bridge chip resides in a cavity machined in the laminate chip carrier. The remaining structure of the DBHi package is similar to a standard flip-chip package. In this study, we focus on the thermal characterization of the DBHi package using measurements and simulations. We determine how much heat generation is allowed for a bridge chip using a conventional cooling solution from the chip top side. The thermal measurements are conducted using a DBHi package with thermal test chips containing heaters and temperature sensors. The chips are heated by supplying power to the heaters and the temperatures on the chips are measured using resistance temperature devices. We then build a simulation model which is calibrated with the thermal measurement results by adjusting the heat transfer coefficient applied to the package lid top. The model comprises two chips, a bridge chip, interconnects between the chips and the bridge, interconnects between the two large chips and a laminate, a Thermal Interface Material (TIM) and a heatspreader (a lid). Based on this simulation model, it is examined how much heat generation is allowed for a bridge chip when its maximum temperature is to remain below 75°C (with an ambient = 40°C). For example, it is simulated that when each chip generates 100 W (total 200 W for two chips), 26.5 W of heat generation is allowed for a bridge chip. We also consider potential cooling solutions from the laminate side.