Surface initiated polymer thin films for the area selective deposition and etching of metal oxides
- Thomas G. Pattison
- Alexander E. Hess
- et al.
- 2020
- ACS Nano
Nick Lanzillo
Title
Research Staff Member
Bio
Nick earned a B.S. in physics from Syracuse University and a Ph.D. in physics from Rensselaer Polytechnic Institute (RPI) in Troy, NY. He joined IBM in 2016 as part of the back-end-of-line (BEOL) integration team and currently works on leading edge technology development with a focus on design-technology co-optimization (DTCO.) Nick was named an IBM Master Inventor in 2020 and again in 2023. He currently serves on the committee for the IEEE International Interconnect Technology Conference.
Publications
Chip Power-Frequency Scaling in 10/7nm Node
- Phil Oldiges
- Reinaldo A. Vega
- et al.
- 2020
- IEEE Access
A Materials Screening Methodology for Scaled Non-Volatile Memory in the AI Era
- Nicholas A. Lanzillo
- R. R. Robison
- 2019
- ANTS 2019
Exploring the Limits of Cobalt Liner Thickness in Advanced Copper Interconnects
- Nicholas A. Lanzillo
- Kisik Choi
- et al.
- 2019
- IEEE Electron Device Letters
Spin-dependent electron scattering in cobalt interconnects
- Nicholas A. Lanzillo
- P. Bhosale
- et al.
- 2019
- Journal of Physics D: Applied Physics
Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
- Takeshi Nogami
- H. Huang
- et al.
- 2019
- VLSI Technology 2019
Electron Transport Across Cu/Ta(O)/Ru(O)/Cu Interfaces in Advanced Vertical Interconnects
- Nicholas A. Lanzillo
- Benjamin D. Briggs
- et al.
- 2019
- Computational Materials Science
An evaluation of Fuchs-Sondheimer and Mayadas-Shatzkes models below 14nm node wide lines
- R. S. Smith
- E. T. Ryan
- et al.
- 2019
- AIP Advances
Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and beyond
- Nicholas A. Lanzillo
- Koichi Motoyama
- et al.
- 2018
- IITC 2018
Modified ALD TaN Barrier with Ru Liner and Dynamic Cu Reflow for 36nm Pitch Interconnect Integration
- P. Bhosale
- J. Maniscalco
- et al.
- 2018
- IITC 2018
Patents
- US
- 11869808
- US
- 11854884
- GB
- 2603346
- US
- 11842961
- GB
- 2600667
- US
- 11823998
- US
- 11804406
- US
- 11791258
- US
- 11756887
- US
- 11749602
Top collaborators
DD
Dan J. Dechene
Director, Semiconductor Enablement
HB
Huiming Bu
Vice President: IBM Semiconductors Global R&D and Albany Operations
TY
Tenko Yamashita
Senior Manager - Advanced Logic Pathfinding Technology
HH
Huai Huang
BEOL Reliability, Quality and Characterization