Selective Incorporation Of Charge For Transistor Channels
- 20 May 2008
Jeffrey W. Sleight received the B.A. degree in physics from Vassar College, Poughkeepsie, NY, USA, in 1988. He received a Fulbright scholarship in 1989 to study at the University of Helsinki's X-Ray Laboratory, Helsinki, Finland. He received the Ph.D. degree in applied physics from Yale University, New Haven, CT, USA, in 1995. His Ph.D. thesis dealt with the physics and fabrication of sub-micron semiconductor structures that exhibit quantum size and charging effects. In 1995, he joined the Device and Interconnect Physics Group, Digital Semiconductor, Hudson, MA, USA, where he worked primarily in the area of silicon on insulator (SOI) device development and modeling. In 1998, he joined IBM, Yorktown Heights, NY, USA, where he has worked in both semiconductor development and research across many areas, ranging from advanced SOI FET scaling, circuit and technology interactions, highly scaled SRAM, and gate all around silicon nanowire FETs. More recently Dr. Sleight's research focus has been in quantum computing, where he works on the understanding of coherence in superconducting qubits, and manages a team focused on experimental studies in this area. He has authored and coauthored more than 100 papers in the areas of semiconductor and quantum device physics, fabrication, and modeling and holds more than 300 U.S. patents.
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