(110) Channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (R ext) engineeringB. YangA. Waiteet al.2007IEDM 2007
Hole transport in nanoscale p-type MOSFET SOI devices with high strainH. NayfehS.-J. Jenget al.2007DRC 2007
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithographyS. NarasimhaK. Onishiet al.2006IEDM 2006
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETsH. NayfehD. Singhet al.2006IEEE Electron Device Letters
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOLW.-H. LeeA. Waiteet al.2005IEDM 2005
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengthsD. SinghJ. Hergenrotheret al.2005IEEE International SOI Conference 2005
Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakageE. GusevC. Cabral Jr.et al.2004IEDM 2004
Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si N-channel MOSFETsGuangrui XiaHasan M. Nayfehet al.2004IEEE Transactions on Electron Devices
Investigation of Scaling Methodology for Strained Si n-MOSFETs Using a Calibrated Transport ModelHasan M. NayfehJudy L. Hoytet al.2003IEDM 2003
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