Investigation of Scaling Methodology for Strained Si n-MOSFETs Using a Calibrated Transport Model

Abstract

The performance, calculated in terms of on-current I on vs. off-current I off, of strained Si n-MOSFETs is compared to bulk (unstrained) Si devices with gate lengths down to 22 nm using hydrodynamic simulations with calibrated strained Si transport models. Strain results in I on enhancement for given I off but increased Coulomb scattering in strained Si super-halo n-MOSFETs with gate lengths approaching 25 nm and surface doping near 6 × 10 18 cm -3 results in reduction of I on enhancement by approximately 10%. Simulations also indicate that the use of a gate electrode material with workfunction larger than n + polysilicon is an attractive approach to achieve desired off-current for strained devices scaled below 25 nm gate length, and for devices with increased strain in the channel (i.e. substrate Ge contents > 20% Ge).