Copper evolution and beyond: Developments in advanced interconnects for future CMOS nodes
Even after 27 years, IBM’s innovation in introducing Cu (copper) damascene technology for BEOL (Back-End-of-Line) in CMOS semiconductor production remains the industry standard for high-performance and low-power logic integrated circuit chip manufacturing. IBM Research has continued to innovate in the field, and published two significant BEOL related papers at the 2024 IEDM conference.
The first paper is an invited paper written by IBM Fellow Daniel Edelstein. It focuses on the advancements and future directions of Cu and post-Cu dual damascene BEOL interconnect technology.
The second paper was co-authored by IBM and Samsung. Written by IBM’s Koichi Motoyama, it discusses the development of a post-Cu, alternative interconnect technology that offers improved resistance-capacitance (RC) performance and reliability.
In the past 50 years, the relentless scaling down of chip feature sizes has been a driving force behind the advancement of semiconductor technology. As a result of Dennard’s scaling law and Moore’s scaling trend, a state-of-the-art Cu wiring technology is presented in this work for 2nm node technology, which is fully vetted with pitch scaled down to an astonishing 24 nm (12 nm line width). Cu damascene technology involves a trench formation in the low-k dielectric, followed by the deposition of diffusion barrier and liner film, and then Cu deposition by electroplating. It has been instrumental in enabling this scaling progress, though most recently, electroplating has been supplanted by an advanced vacuum “reflow” process.
As shown in the picture below, the resistance of the Cu line increases due to the diminishing volume fraction of the conductor (Cu) in the line as the metal pitch scales, considering the fraction of the relatively more resistive materials, barrier, and liner material.
To lower the resistivity of the line and increase the volume of Cu, the barrier and liner can be thinned down. However, this thinning process degrades the barrier property, which is responsible for blocking Cu diffusion into the dielectric. As a result, the dielectric reliability (TDDB) suffers. Innovations are needed to increase the volume of Cu in the narrow line without compromising the barrier property and TDDB reliability. On the other hand, the thinning of liner can lead to an increase in void formation tendency in Cu lines, which in turn can degrade the reliability of Cu lines. This issue is particularly pronounced when using ultra low-k dielectric films, which are typically softer than SiO2 films.
In this paper, IBM introduces an advanced low-k dielectric (ALK) material, which offers unparalleled mechanical strength, plasma-induced damage (PID) resistance, adhesion, and Cu-O2 diffusion barrier properties. This cutting-edge ALK film enables continued Cu barrier scaling for lower line resistance while significantly improving patterning of trenches without compromising the reliability. The accompanying image demonstrates the remarkable damage resistance of the ALK film.
In Figure 2, the blue data points extrapolate to much longer lifetimes (T63) in the graph. It illustrates the superiority of ALK films over conventional SiCOH materials in terms of dielectric film reliability (TDDB). Below, Figure 3 shows that most of the data points are on the right-hand side (longer lifetime) of the green/pink/blue reference lines. This means that ALK films enable scaled barrier or liner films to meet the Cu line reliability (EM, electromigration) target, which is crucial for high-performance and low-power logic IC chip manufacturing. This information highlights the significant benefits of using ALK films in BEOL interconnect technology.
The paper also highlights the potential of rhodium (Rh) damascene technology as a promising alternative to existing Cu damascene technology. Rh (or iridium) has been identified as a material with low surface scattering behavior and a low propensity for oxidation, which allows for thinner barrier or even barrierless line formation. The IBM team's work in demonstrating the electroplating of Rh and the CMP process for Rh damascene technology is a significant milestone. Although Rh is very rare and expensive material, and so not widely considered in the industry, the cost evaluation and analysis in the paper suggest that only scant amounts are actually used for these nanoscale wiring levels, and for any unused waste, there are active recycling methods to help reduce its cost to a reasonable level. The adoption of Rh material in interconnect structures has the potential to significantly enhance performance and reliability, making Rh damascene technology an intriguing area of research and development.
In collaboration with Samsung’s R&D center, IBM Research's Pathfinding team has been actively engaged in the development of cutting-edge interconnect technology below the 20nm pitch, to overcome the limitations of Cu based interconnect technology. Ru interconnects have been extensively evaluated as a promising solution to achieve lower line resistance and improved electromigration (EM) performance for future technologies. Our team has previously presented a world’s first Ru top-via structure (where the via locates above line) with an airgap at the IEDM conference in 2022, showcasing our advancements in this area. This year’s IEDM paper discusses about the next step maturity of the technology: Reliability.
Figure 5 shows cross-sectional transmission electron microscope (TEM) image of a fully subtractive Ru top-via interconnect with airgap. The top-via integration enables us to fully placement airgaps automatically, without interference of vias in the airgap. In addition, this integration scheme also allows an improved dielectric breakdown voltage between vias and adjacent line above even when there are overlay issues between them. In the conventional damascene process flow, airgap formation requires additional steps, such as the removal of the dielectric film between metal lines, which can potentially impact the reliability of the metal lines and via encroachment issues from the top.
In the conventional damascene integration scheme, one of the major concerns is overall capacitance increase, due to a low-k damage caused by plasma etching during patterning processes. However, in the top-via integration scheme, low-k damage by plasma etch does not occur, since the gaps between Ru lines are filled with fresh low-k or airgap after Ru line and top-via fabrication. As shown in Figure 6, compared to conventional damascene interconnect with dielectric damage, top-via interconnects can reduce the capacitance by around 9% at 18 nm metal pitch due to having pristine low-k without plasma damage. We also achieved an additional 14% reduction in capacitance by implementing an airgap in the top-via structure. This is a very important benefit for the future technology nodes where capacitance scaling becomes more and more important for the highly scaled devices such as stacked FET.
The embedded airgap is found to be easy to implement and yet effective to reduce the capacitance between metal lines. However, it has been one of the big questions from the industry how well the embedded airgap performs with respect to the incumbent low-k dielectric material in terms of reliability. Figure 7 shows TDDB results on damascene Cu interconnect with low-k (where SiCOH k=2.7) and subtractive Ru interconnects with airgap at the same metal pitch (line-to-line space: 12 nm). Subtractive Ru interconnects with an airgap showed longer lifetime than damascene Cu interconnect with low-k dielectric while passing the technology target. On the other hands, it has been widely believed that the EM of Ru lines would be superior based on Ru’s robust material properties. EM test for two-level Ru top-via interconnect was performed and the result is shown in Fig. 8. No EM failure (from resistance increase) was observed up to 1800 hours, except in one sample, which means that Ru is much better than our best Cu data at similar physical dimension, since test condition for this Ru interconnect is much severer than Cu EM test.
For the first time in the industry, we demonstrated the reliability (TDDB and EM) of 18nm pitch subtractive Ru with embedded airgap and top-via. As a result, we concluded that the fully subtractive top-via interconnect with airgap is a promising candidate as post-Cu alternative metal interconnects for future CMOS technologies.