A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity
- Lei Zhao
- Junyao Tang
- et al.
- 2024
- IEEE Journal of Solid-State Circuits
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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
- Monodeep Kar
- Joel Silberman
- et al.
- 2024
- IEEE Journal of Solid-State Circuits
Circuit and physical design of the zenterprise™ ec12 microprocessor chips and multi-chip module
- James Warnock
- Yuen Chan
- et al.
- 2014
- IEEE Journal of Solid-State Circuits
An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
A 2.6 mW/Gbps 12.5 Gbps RX with 8-Tap switched-capacitor DFE in 32 nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
Dual-loop system of distributed microregulators with high DC accuracy, load response time below 500 ps, and 85-mV dropout voltage
- John F. Bulzacchelli
- Zeynep Toprak-Deniz
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
Exploiting combinatorial redundancy for offset calibration in flash ADCs
- Gokce Keskin
- Jonathan Proesel
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
A fully-integrated 16-element phased-array receiver in SiGe BiCMOS for 60-GHz communications
- Arun Natarajan
- Scott K. Reynolds
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
POWER7™, a highly parallel, scalable multi-core high end server processor
- Dieter F. Wendel
- Ron Kalla
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- John Barth
- Don Plass
- et al.
- 2011
- IEEE Journal of Solid-State Circuits