Overlay as the key to drive wafer scale 3D integration
- Steven E. Steen
- Douglas LaTulipe
- et al.
- 2007
- Microelectronic Engineering
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107 results for David J. Frank
Three-dimensional integrated circuits
- Anna W. Topol
- Douglas C. La Tulipe Jr.
- et al.
- 2006
- IBM J. Res. Dev
Optimizing CMOS technology for maximum performance
- David J. Frank
- Wilfried Haensch
- et al.
- 2006
- IBM J. Res. Dev
High-performance CMOS variability in the 65-nm regime and beyond
- Kerry Bernstein
- David J. Frank
- et al.
- 2006
- IBM J. Res. Dev
Universal tunneling behavior in technologically relevant P/N junction diodes
- Paul M. Solomon
- Jason Jopling
- et al.
- 2004
- Journal of Applied Physics
Frequency dependent characterization of transport properties in carbon nanotube transistors
- J. Appenzeller
- D.J. Frank
- 2004
- Applied Physics Letters
Design considerations for CMOS near the limits of scaling
- David J. Frank
- Yuan Taur
- 2002
- Solid-State Electronics
Power-constrained CMOS scaling limits
- David J. Frank
- 2002
- IBM J. Res. Dev
Device scaling limits of Si MOSFETs and their application dependencies
- David J. Frank
- Robert H. Dennard
- et al.
- 2001
- Proceedings of the IEEE
Analysis of the design space available for high-k gate dielectrics in nanoscale MOSFETs
- David J. Frank
- Hon-Sum P. Wong
- 2000
- Superlattices and Microstructures