Probing the limits of silicon-based nanoelectronics

Abstract

The ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption. CMOS (Complementary Metal-Oxide-Semiconductor) devices with 100 nm channel lengths offer a 2X performance gain over 0.25 μm technology at a reduced power supply as well as the potential for a 20X reduction in active power at comparable performance levels. Continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations. Overcoming these limitations will require technological innovation in both device design and fabrication.