Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs

Abstract

We present a simulation-based analysis of the device design and circuit performance trade-offs between short channel immunity and parasitic device capacitances of sub-0.1 μm double-gate SOI MOSFET's. We demonstrate that perfect alignment of the bottom gate to the top gate is not necessary to achieve adequate short channel immunity but is required to maintain short gate delays. Double-gate MOSFET device design guidelines are provided.