Scaling silicon MOS devices to their limits

Abstract

The scaling of silicon CMOS (Complementary Metal-Oxide-Semiconductor) devices to 100 nm channel lengths offers significant potential for high speed circuit performance gains at low levels of power consumption. Continued miniaturization beyond 100 nm dimensions faces various daunting challenges. Overcoming these challenges will require technological innovation in device design as well as fabrication techniques. If these challenges can be met successfully, there is room to scale silicon technology well into the nanometer regime.