Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020
Publications
59 results for B. Haran
Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact over Active Gate (COAG) for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- VLSI Technology 2020
Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices
- Shogo Mochizuki
- B. Colombeau
- et al.
- 2020
- VLSI Technology 2020
Selective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies
- Ruqiang Bao
- K. Watanabe
- et al.
- 2020
- VLSI Technology 2020
Composite Interconnects for High-Performance Computing beyond the 7nm Node
- P. Bhosale
- S. Parikh
- et al.
- 2020
- VLSI Technology 2020
High quality interfacial layer formation for Si0.75Ge0.25 (100) high-k metal gate stack
- S. Siddiqui
- R. Galatage
- et al.
- 2020
- Microelectronic Engineering
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
- Nicolas Loubet
- T. Devarajan
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
- Takeshi Nogami
- H. Huang
- et al.
- 2019
- VLSI Technology 2019