Publications

48 results for Mukesh Khare

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
- - A. Khakifirooz
  - Kangguo Cheng
  - et al.
- 2012
- VLSI Technology 2012
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- - S. Krishnan
  - U. Kwon
  - et al.
- 2011
- IEDM 2011
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- - Q. Liu
  - Frederic Monsieur
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Technology 2011
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- - Chung-Hsun Lin
  - Wilfried Haensch
  - et al.
- 2011
- VLSI Technology 2011
Full metal gate with borderless contact for 14 nm and beyond
- - Soon-Cheon Seo
  - L.F. Edge
  - et al.
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Circuits 2011
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- VLSI Technology 2011
Ultra-thin Body and BOX (UTBB) device for aggressive scaling of CMOS technology
- - Q. Liu
  - A. Yagishita
  - et al.
- 2011
- CSTIC 2011
Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- CSTIC 2011