Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
- D. Singh
- J. Sleight
- et al.
- 2005
- IEDM 2005
Publications
39 results for Dureseti Chidambarrao
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths
- D. Singh
- J. Hergenrother
- et al.
- 2005
- IEEE International SOI Conference 2005
Controlled nucleation of dislocations by a spatially localized stress field
- M. Kammler
- D. Chidambarrao
- et al.
- 2005
- Applied Physics Letters
Dislocation modeling for the microelectronics industry
- K.W. Schwarz
- D. Chidambarrao
- 2005
- Materials Science and Engineering: A
Retardation of arsenic diffusion in silicon-germanium by co-implantation
- Omer Dokumaci
- Paul Ronsheim
- et al.
- 2004
- ECS Meeting 2004
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications
- J. Beintner
- Y. Li
- et al.
- 2004
- IEEE Electron Device Letters
Moisture and oxygen uptake in Low K/ copper interconnect structures
- T.M. Shaw
- D. Jimerson
- et al.
- 2003
- ADMETA 2003
On the retention time distribution of dual-channel vertical DRAM technologies
- J. Beintner
- Y. Li
- et al.
- 2003
- VLSI-TSA 2003