High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Publications
38 results for Dureseti Chidambarrao
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Controlled nucleation of dislocations by a spatially localized stress field
- M. Kammler
- D. Chidambarrao
- et al.
- 2005
- Applied Physics Letters
Dislocation modeling for the microelectronics industry
- K.W. Schwarz
- D. Chidambarrao
- 2005
- Materials Science and Engineering: A
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Retardation of arsenic diffusion in silicon-germanium by co-implantation
- Omer Dokumaci
- Paul Ronsheim
- et al.
- 2004
- ECS Meeting 2004
Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications
- J. Beintner
- Y. Li
- et al.
- 2004
- IEEE Electron Device Letters
Moisture and oxygen uptake in Low K/ copper interconnect structures
- T.M. Shaw
- D. Jimerson
- et al.
- 2003
- ADMETA 2003
Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies
- D. Chidambarrao
- K. McStay
- et al.
- 2003
- VLSI-TSA 2003
On the retention time distribution of dual-channel vertical DRAM technologies
- J. Beintner
- Y. Li
- et al.
- 2003
- VLSI-TSA 2003