An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS
- A. Serdar Yonar
- Pier Andrea Francese
- et al.
- 2022
- VLSI Technology and Circuits 2022
Publications
85 results for Matthias Brändli
A system design approach toward integrated cryogenic quantum control systems
- Mridula Prathapan
- Peter Mueller
- et al.
- 2022
- WOLTE 2022
HERMES-Core-A 1.59-TOPS/mm2PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs
- Riduan Khaddam-Aljameh
- Milos Stanisavljevic
- et al.
- 2022
- IEEE JSSC
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
- R. Khaddam-Aljameh
- M. Stanisavljevic
- et al.
- 2021
- VLSI Technology 2021
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
- Riduan Khaddam-Aljameh
- Milos Stanisavljevic
- et al.
- 2021
- VLSI Circuits 2021
Experimental efficiency evaluation of stacked transistor half-bridge topologies in 14 nm cmos technology
- Pedro André Martins Bezerra
- Florian Krismer
- et al.
- 2021
- Electronics (Switzerland)
An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS
- Marcel Kossel
- Vishal Khatri
- et al.
- 2021
- ISSCC 2021
An In-Comparator Aperture-Time Equalization in a 7-nm FinFET CMOS 40-Gb/s Receiver
- Abdullah Serdar Yonar
- Pier Andrea Francese
- et al.
- 2020
- IEEE SSC-L
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
- Gain Kim
- Marcel Kossel
- et al.
- 2020
- IEEE JSSC
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET
- Gain Kim
- Lukas Kull
- et al.
- 2019
- A-SSCC 2019