Digital SNN in 5 nm FinFET CMOS with latency-reducing hybrid spiking scheme operated at 2.6 GHz
- Marcel Kossel
- Giovanni Cherubini
- et al.
- 2025
- ICM 2025
Publications
87 results for Matthias Brändli
A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET
- Jaewon Lee
- Pier-Andrea Francese
- et al.
- 2025
- ISSCC 2025
A DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET
- Seoyoung Jang
- Marcel Kossel
- et al.
- 2025
- ISSCC 2025
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2025
- IEEE Transactions on Very Large Scale Integration VLSI Systems
A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET
- Jaewon Lee
- Pier-Andrea Francese
- et al.
- 2025
- IEEE Journal of Solid State Circuits
A NRZ/PAM4 SST TX in 5nm FinFET CMOS with 3-tap FFE and 0.7pJ/b efficiency at 100 Gb/s PAM4
- Marcel Kossel
- Matthias Brandli
- et al.
- 2024
- ESSERC 2024
A 40 GS/s 8b-DAC SST-TX in 7 nm FinFET CMOS for cryogenic quantum applications with 32kB SRAMbased RF-DDS AWG
- Marcel Kossel
- Matthias Brandli
- et al.
- 2024
- ESSERC 2024
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- ISCAS 2024
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with 1Vppd Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS
- Zeynep Toprak-Deniz
- Timothy O. Dickson
- et al.
- 2024
- VLSI Technology and Circuits 2024
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration
- Tod Dickson
- Zeynep Toprak Deniz
- et al.
- 2024
- CICC 2024