Publication
ISSCC 2021
Conference paper

An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS

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Abstract

Digital-to-analog converter (DAC)-based transmitters are suited to support different modulation formats (e.g., NRZ, PAM-4, OFDM), long-channel equalization (incl. roaming taps) or even amplitude reduction for reflection mitigation at short channels. Compared to transmitters with a conventional FFE, a less complex and more uniform high-speed analog frontend can be designed in a DAC TX if the number of taps is large (e.g., >5) because the equalization is performed in the digital signal processing (DSP) unit running at sub-rate. However, this imposes the challenge of achieving low latency and power consumption, particularly at high resolution (e.g. 8b) and speed. The DAC TX presented here addresses these challenges with a table-based FFE approach with input gating of the combinatorial logic in the DSP. In the analog part of the DAC TX power reduction is achieved by utilizing metal gate poly resistors for compact layout with fewer parasitics and a DAC-weight unit scaling for reduced clock load. Across a full lot of 5 split wafers (FF, FS, TT, SF, SS) the measured power efficiency at l00Gb/s PAM-4 ranges from 1.30 to 1. 42pJl b at a supply voltage of 900mV with all FFE taps enabled.

Date

13 Feb 2021

Publication

ISSCC 2021

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