VLSI Technology and Circuits 2022
Conference paper

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS

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A 56 GS/s 8-bit asynchronous SAR ADC fabricated in 4nm CMOS technology is demonstrated. The 16x4 interleaved ADC uses a novel bootstrapping technique and a class-AB follower in the 1st rank interleaver. It achieves a broad input common-mode (CM) range; from 0.3V to 0.6V, the total harmonic distortion stays below -52dB at 4.1 GHz with -0.2dBFS amplitude at 0.8VPPD maximum full scale. The ADC includes analog foreground calibration means for offset, gain, skew, and bandwidth. The measured ENOB is 6.5 at low frequency and stays above 5.2 up to Nyquist frequency. The bandwidth is higher than 27 GHz. The ADC uses a single 0.8V supply voltage and achieves an efficiency of 47 fJ/conv.step.

Authors’ notes

Per lane data rate in wireline receivers shows an aggressive upwards trend due to distributed computing over the last decades. Data rates for various communication standards double approximately every four years [1]. Data-intensive applications such as machine learning and AI are likely to strengthen this trend and lead to the adoption of a new set of modulation techniques and more stringent latency requirements. Furthermore, Internet of Things devices lead to a substantial increase in data center traffic, required to meet the tight bandwidth demand. In order to meet the throughput requirement of the next generation of data-centric applications, the bandwidth efficiency must increase since the physical channels do not scale as CMOS nodes.

This leads to the emergence of multi-level signaling such as PAM4, which is the mainstream choice currently targeting data rates above 100 Gb/s. The future will bring higher order modulation formats that utilizes frequency domain such as OFDM. The decreased SNR, due to complex modulation schemes in addition to the flexibility required to run the SerDes at different conditions, favors the ADC-DSP-based RX architectures. This allows the implementation of complex equalization strategies in digital domain and eases future adoption with technology scaling.

Our approach

To meet the aforementioned requirements of the next-generation wireline ADC-DSP based receivers, we have designed a 56 GS/s, 8-bit time interleaved ADC in Samsung 4nm (4lpp) technology together with Samsung Foundry IP Development Team. The ADC, which is powered by a single 0.8V supply, has a 16x4 interleaving factor as shown in Figure 1a to have an optimum tradeoff between the conversion time and the bandwidth.

Figure 1a. ADC architecture.
Fig 1a. ADC architecture.

With increasing interleaving factors, the interleaver specifications become more stringent. Taking this into consideration, we have designed a bootstrapped switch for the first rank interleaver, which has a high tracking bandwidth with a broad input common mode voltage range (Fig. 1b). Moreover, we have utilized a modified class AB follower (Fig. 1c) as a first rank buffer which also addresses DC baseline wander.

Considering the balance between the speed and metastability, asynchronous successive approximation register (ASAR) ADC architecture is chosen as a sub-ADC (Fig. 1d). Differential memory cells are used within the ASAR to increase the robustness against the forbidden states and metastability.

Figure 1b. (left) 1st Rank T & H; Figure 1c (right) - modified class-AB follower as 1st RANK buffer.
Fig 1b. (left) 1st Rank T & H; Figure 1c (right) - modified class-AB follower as 1st RANK buffer.
Figure 1d. ASAR ADC.
Figure 1d. ASAR ADC.

Interleaving spurs are a critical limitation for time-interleaved ADCs degrading the resolution considerably. To address this, we have added a full foreground calibration capability to correct offset, gain, bandwidth and skew mismatch on chip.

The output data of each sub-ADC are sampled by 256 sample shift registers, which allows a total of 16k samples to be shifted out.


The layout and chip micrograph of the designed ADC are shown in Fig 2a. It achieves a state-of-the-art FoM of 47 fJ/conv.step with a total power dissipation of 240mW. The measured bandwidth is greater than 27 GHz. The ADC active area occupies 0.078mm.2

Sine tests result can be observed in Fig 3. The SNDR and SFDR are measured with a 0.2dB backoff from a 0.8VPPD (Fig. 3a). INL curve indicates a superior linearity achieved in Fig 3b. In Fig 3c the total harmonic distortion (THD) profile is shown for different input common mode values. The low frequency THD stays above -52dB in a 0.3V range which proves the robustness of the interleaver design against common mode variations. Finally, Fig. 3d shows the low frequency spectrum with 6.5 ENOB and an impressive THD of -60.6 dB.

Fig 3. 4nm die photo and layout.
Fig 3. 4nm die photo and layout.
Figures 3a-3d. Sine test results.
Figs 3a-3d. Sine test results. Top left Fig 3a: SNDR and SFDR measurements. Top right Fig 3b: INL curve. Bottom left Figure 3c: Total Harmonic Distortion (THD) profile. Bottom right Fig 3d: Low Frequency spectrum.

The ADC is also tested using different modulation formats. For this purpose, the channel is extracted and equalized using FFE on the transmit side. The results of PAM4 and OFDM tests are shown in Fig 4. Fig 4a shows a 112 Gb/s PAM4 eye diagram captured with the ADC. It achieves 22dB SNDR and the captured bits are error free. Another promising experiment is with the 165Gb/s OFDM modulation the constellation of which is shown in Fig 4b.

The average channel SNDR is 22.6dB and the captured data with block coded modulation with an inner binary product code and outer RS KR4 code is error free. These measurements demonstrate the success of the designed ADC with spectrally efficient modulation formats.

Fig 4a. 112Gb/s PAM4 eye diagram.
Fig 4a. 112Gb/s PAM4 eye diagram.
Fig 4b. 165Gb/s OFDM constellation.
Fig 4b. 165Gb/s OFDM constellation.

Future work

Some possible directions for future related research include:

  • Developing and integrating the DSP targeting the modulation format to be used.
  • Designing a high bandwidth Analog Frontend (AFE) to be used with the current architecture.
  • Exploring different sub-ADC architectures such as time domain techniques to increase the per channel sampling speed to reduce the interleaving factor and latency.

[1] S. Mirabbasi, L. C. Fujino and K. C. Smith, "Through the Looking Glass—The 2022 Edition: Trends in solid-state circuits from ISSCC," in IEEE Solid-State Circuits Magazine, vol. 14, no. 1, pp. 54-72, winter 2022, doi: 10.1109/MSSC.2021.3128243.