FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys
- Oleg Gluschenkov
- Zuoguang Liu
- et al.
- 2016
- IEDM 2016
Publications
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43 results for Tenko Yamashita
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Air spacer for 10nm FinFET CMOS and beyond
- K. Cheng
- C. Park
- et al.
- 2016
- IEDM 2016
Understanding and mitigating High-k induced device width and length dependencies for FinFET replacement metal gate technology
- Takashi Ando
- Tenko Yamashita
- et al.
- 2015
- IEDM 2015
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
- Abhijeet Paul
- Andres Bryant
- et al.
- 2013
- IEDM 2013
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
- H. Kawasaki
- V.S. Basker
- et al.
- 2009
- IEDM 2009
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
EUV Double Patterning Solution for Subtractive Metal Patterning at 18nm Pitch
- Chris Penny
- Koichi Motoyama
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Sub-10-9 Ω-cm2 n-Type Contact Resistivity for FinFET Technology
- Hiroaki Niimi
- Zuoguang Liu
- et al.
- 2016
- IEEE Electron Device Letters
Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact over Active Gate (COAG) for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- VLSI Technology 2020