Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures
- Zuoguang Liu
- Heng Wu
- et al.
- 2019
- VLSI Technology 2019
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43 results for Tenko Yamashita
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
- Miaomiao Wang
- Jingyun Zhang
- et al.
- 2019
- IRPS 2019
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
Technique for Asymmetric Source/Drain Resistance Extraction on a Single Gate Length MOSFET
- Phil Oldiges
- Chen Zhang
- et al.
- 2018
- SISPAD 2018
FinFET external resistance analysis by extended shift-and-ratio method
- Chen Zhang
- Zuoguang Liu
- et al.
- 2018
- IEEE T-ED
Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet
- Chun Wing Yeung
- Jingyun Zhang
- et al.
- 2018
- IEDM 2018
Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology
- S. Reboh
- R. Coquand
- et al.
- 2018
- Applied Physics Letters
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
Dual beam laser annealing for contact resistance reduction and its impact on VLSI integrated circuit variability
- Zuoguang Liu
- Oleg Gluschenkov
- et al.
- 2017
- VLSI Technology 2017
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
- N. Loubet
- T.B. Hook
- et al.
- 2017
- VLSI Technology 2017