Publications

44 results for Tenko Yamashita

NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- - Shay Reboh
  - Chen Zhang
  - et al.
- 2025
- VLSI Technology and Circuits 2025
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- - Chen Zhang
  - Seungmin Song
  - et al.
- 2024
- IEDM 2024
Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- - Koichi Motoyama
  - Jaemyung Choi
  - et al.
- 2024
- IEDM 2024
Backside power distribution for nanosheet technologies beyond 2nm
- - Ruilong Xie
  - Wonhyuk Hong
  - et al.
- 2024
- VLSI Technology and Circuits 2024
EUV Double Patterning Solution for Subtractive Metal Patterning at 18nm Pitch
- - Chris Penny
  - Koichi Motoyama
  - et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- - C. J. Penny
  - Koichi Motoyama
  - et al.
- 2022
- IEDM 2022
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- - H. Jagannathan
  - B. Anderson
  - et al.
- 2021
- IEDM 2021
Improved Air Spacer for Highly Scaled CMOS Technology
- - Kangguo Cheng
  - Chanro Park
  - et al.
- 2020
- IEEE Transactions on Electron Devices
Improved Air Spacer Co-Integrated with Self-Aligned Contact (SAC) and Contact over Active Gate (COAG) for Highly Scaled CMOS Technology
- - Kangguo Cheng
  - Chanro Park
  - et al.
- 2020
- VLSI Technology 2020
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- - J. Zhang
  - S. Pancharatnam
  - et al.
- 2019
- IEDM 2019