Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Publications
46 results for Tenko Yamashita
NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
First Demonstration of 16nm Pitch Subtractive Ru Interconnects for Advanced Technology Nodes
- C. Penny
- K. Motoyama
- et al.
- 2025
- IITC 2025
Fully subtractive Ru Topvia interconnects with minimum 9 nm-space airgap for RC performance and reliability enhancement as post-Cu interconnects
- Koichi Motoyama
- Jaemyung Choi
- et al.
- 2024
- IEDM 2024
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Backside power distribution for nanosheet technologies beyond 2nm
- Ruilong Xie
- Wonhyuk Hong
- et al.
- 2024
- VLSI Technology and Circuits 2024
EUV Double Patterning Solution for Subtractive Metal Patterning at 18nm Pitch
- Chris Penny
- Koichi Motoyama
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Improved Air Spacer for Highly Scaled CMOS Technology
- Kangguo Cheng
- Chanro Park
- et al.
- 2020
- IEEE Transactions on Electron Devices