Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Conference paper
Jim Mazza
Title
System/Design Technology Co-Optimization Hardware Developer | IBM Master Inventor
Publications
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Conference paper
Patents
- US
- 12733261
- US
- 12727179
- US
- 12701745
- US
- 12696533
- US
- 12622260
Top collaborators
DD
Dan J. Dechene
Anderon, Head of Foundry Business
HB
Huiming Bu
Vice President: IBM Semiconductors Global R&D and Albany Operations
TY
Tenko Yamashita
Senior Manager - Advanced Logic Pathfinding Technology
DG
Dechao Guo
Vice President, Advanced Logic Technology R&D