A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology
- U. Kwon
- K. Wong
- et al.
- 2012
- VLSI Technology 2012
Publications
Date
Featured collections
Popular topics
45 results for M. Chudzik
The materials and integration challenge in implementing & scaling high-k/metal gate transistors for high performance CMOS
- Michael Chudzik
- 2011
- ADMETA 2011
Characterization of novel TiN/HfO2 metal insulator semiconductor stack for 32nm eDRAM
- Puneet Goyal
- Sneha Gupta
- et al.
- 2010
- IEEE International SOI Conference 2010
Comparative study of CVD TiN vs. ALD TiN for contact metallization in 32nm node and beyond
- Valli Arunachalam
- Filippos Papadatos
- et al.
- 2010
- ADMETA 2010
Advanced metallization developments for 32-nm node CMOS technology contact architecture
- Doug H. Lee
- Valli Arunachalam
- et al.
- 2009
- ADMETA 2009
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper
- B. Greene
- Q. Liang
- et al.
- 2009
- VLSI Technology 2009
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
- M. Chudzik
- B. Doris
- et al.
- 2007
- VLSI Technology 2007
Challenges in FEOL logic device integration for 32 nm technology node and beyond
- Dae-Gyu Park
- M. Chudzik
- et al.
- 2007
- ECS Meeting 2007