IEDM 2009
Conference paper

Scaling deep trench based eDRAM on SOI to 32nm and beyond

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A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-κ metal gate access transistor and high-κ node dielectric for the deep trench storage capacitor. We also describe the technology advancements required to scale the deep trench as well as the access transistor for optimal cell retention and performance. A clear scaling path is seen for the 22nm technology node. © 2009 IEEE.