A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V
- Elisa Sacco
- Pier Andrea Francese
- et al.
- 2017
- VLSI Circuits 2017
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59 results for Lukas Kull
A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET
- Danny Luu
- Lukas Kull
- et al.
- 2017
- VLSI Circuits 2017
Measurement of high-speed ADCs
- Lukas Kull
- Danny Luu
- 2017
- CICC 2017
CMOS ADCs Towards 100 GS/s and beyond
- Lukas Kull
- Danny Luu
- et al.
- 2016
- CSICS 2016
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Design considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
A 0.6-1.2 THz monolithic imaging array
- Dan Corcos
- Noam Kaminski
- et al.
- 2015
- IRMMW-THz 2015
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- Hazar Yueksel
- Lukas Kull
- et al.
- 2015
- ESSCIRC 2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- Alessandro Cevrero
- Cosimo Aprile
- et al.
- 2015
- VLSI Circuits 2015
Challenges in implementing high-speed, low-power ADCs in CMOS
- Lukas Kull
- 2015
- OFC 2015