Publication
OFC 2015
Conference paper

Challenges in implementing high-speed, low-power ADCs in CMOS

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Abstract

Challenges of CMOS ADC implementations for 100 Gb/s optical communication systems and beyond are highlighted. Limitations and opportunities of architectures and circuits are discussed based on a 56-90 GS/s 8 bit ADC in 32 nm SOI CMOS.

Date

Publication

OFC 2015

Authors

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