About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
CompEuro 1989
Conference paper
VLSI display controller and processor
Abstract
The heart of the IBM PS/2 Image Adapter is a VLSI display controller and processor chip utilizing an advanced 1-μm standard-cell CMOS technology. This chip is 9.4 mm square and contains the standard-cell equivalent of 40,000 two-input NAND gates, organized as a matrix of 27,000 wireable cells. It is packaged in a 194-pin IBM pin grid array and consumes approximately 1 W. The display controller and processor chip contains most of the digital logic which gives the Image Adapter its high performance and function. It provides a programmable adapter which can be personalized for image, text, or graphics simply by providing a new microcode load for the on-chip processor. The Image Adapter performs algorithms such as image compression and graphics rotation at rates comparable to hardware, while retaining the flexibility of programmable microcode. A complete set of tools is provided for the processor, including a C language compiler, assembler, linker, simulator, and debugger.