VLSI architectures for metric normalization in the Viterbi algorithm

Abstract

In the realization of Viterbi decoders with finite precision arithmetic, the values of the survivor metrics computed by the add-compare-select (ACS) recursion must remain within a finite numerical range to avoid catastrophic overflow (or underflow) situations. In the present work, the authors compare several metric normalization techniques which are suitable for VLSI implementations with fixed-point arithmetic. The modulo technique is found to be the most local and uniform approach. An efficient VLSI design of the ACS units based on this technique is discussed. The modified comparison rule is found to produce a more efficient ACS architecture than previous results based on subtraction.