Understanding and Measuring the Jitter Generated by Digital CMOS Gates

Abstract

CMOS logic gates inevitably generate timing jitter as they propagate digital signals. A portion of this jitter is a fundamental property of CMOS gates which cannot be eliminated or reduced, and thereby imposes a lower limit to achievable circuit jitter. The value of this intrinsic jitter of each gate is very small, but can be measured with a dedicated test circuit composed of chains of CMOS inverters. The measurements of the circuit also lead to the determination of the component of jitter which is caused by noise of the power supply which operates the gates.