The need for low resistance interconnects in future high-speed systems

Abstract

As logic technology advances toward higher speeds and higher levels of integration, the problem of interconnects becomes more acute. This is because, per unit length, the resistance of a wire increases as all dimensions are reduced whereas its capacitance remains constant. This presentation will consider the statistics of wiring a large chip, based on Rent's rule, and derive relationships for wire resistance and current density. The efficacy of solutions to the wiring bottleneck, such as the use of a wiring hierarchy, and the use of repeaters, will be examined. Using these results it will be shown that a 77K ambient will be highly desirable for a future high speed computer, when circuit densities will be greater than 100,000 circuits/cm2 and circuit delays less than 100ps. The speed advantage of the 77K computer over the room temperature version will scale as √ρτCKT where ρ is the wire resistance and τckt is the circuit delay. The advantage of superconducting wires, and requirements on current density, will also be discussed in this context.