The effect of dynamic power management on mid-frequency and low-frequency power supply noise

Abstract

As device sizes continue to shrink and circuit complexity continues to grow, power has become the limiting factor in today's processor designs. This paper describes a hierarchical scalable power supply noise analysis methodology to simulate the switching events that arise from the ubiquitous use of clock gating, power gating, frequency scaling, and other power management techniques. By accurately extracting and modeling the electrical characteristics of both the package and chip design, our multi-core multi-voltage-domain transient noise analysis ensures the power and signal integrity of our design under different workloads and operating frequencies. A series of case studies will be presented to illustrate the effect of power management operations on transient noise and the design of a power management control unit to contain voltage droop. Copyright © 2010 American Scientific Publishers All rights reserved.