Bowen Zhou, Bing Xiang, et al.
SSST 2008
The IBM POWER4 processor is a 174-million-transistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.
Bowen Zhou, Bing Xiang, et al.
SSST 2008
Preeti Malakar, Thomas George, et al.
SC 2012
B.K. Boguraev, Mary S. Neff
HICSS 2000
Liat Ein-Dor, Y. Goldschmidt, et al.
IBM J. Res. Dev