1D semiconducting nanowires (NWs) have gained great attention as they are one of the best-defined classes of nanoscale building blocks for bottom-up assembly of next generation electronic, sensing, and optoelectronic devices, whether in the form of individual NWs  or their arrays . While the growth based on physical epitaxy results in the high-quality NWs, due to the challenging harvesting and aligning to the existing features on a chip, their integration with the silicon-based platform is cost and time consuming. In order to utilize the advantages of semiconducting nanowires on silicon, an integration method called template-assisted selective epitaxy (TASE) was developed, which combines selective epitaxy and growth direction control. This technology in combination with a metal-organic chemical vapor deposition (MOCVD) was successfully applied for monolithic integration of for example InAs and GaAsSb on silicon or silicon-on-insulator (SOI) substrates resulting in a wide range of electronic devices [3, 4]. In this work we will explore the possibilities of III-V nanowires integration on Si platforms, including alternative synthesis routes for materials which are challenging to grow with physical epitaxy methods . Acknowledgements The research was carried out thanks to the financial support of the Marie Skłodowska-Curie Action H2020 EU TECNO (894326).  M.F. Fatahilah, F. Yu, K. Strempel, et al. Sci Rep 9, 10301 (2019).  G. Zhang, H. Zeng, J. Liu, et al, Analyst 146, 6684 (2021).  D. Cutaia, K. Moselund, M. Borg, et al. IEEE J Electron Dev Soc 3, 176 (2015).  A. Schenk, S. Sant, K. Moselund, et al. In Proc. Simulation of Semiconductor Processes and Devices (SISPAD) (2017).  K.E. Hnida-Gut, M. Sousa, S. Redit, et al. Fron Chem (2021) (accepted).