Yi-Bo Liao, Meng-Hsueh Chiang, et al.
Microelectronics Journal
This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme. © 2009 IEEE.
Yi-Bo Liao, Meng-Hsueh Chiang, et al.
Microelectronics Journal
Keunwoo Kim, Koushik K. Das, et al.
ISLPED 2004
Jente B. Kuang, J. Schaub, et al.
CICC 2010
Jie Deng, Keunwoo Kim, et al.
ISQED 2007