About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
International Journal of Electronics
Paper
Process/physics-based threshold voltage model for nano-scaled double-gate devices
Abstract
Compact physics/process-based model for threshold voltage in double-gate devices is presented. Predominant short-channel effects for double-gate devices, which are drain-induced barrier lowering (DIBL) and short-channel-induced barrier lowering (SCIBL), are physically analysed and modeled to be applicable to SPICE-compatible circuit simulators. The short-channel models are also developed for bulk-Si device and compared to those of double-gate devices. The validity and predictability of the models are demonstrated and confirmed by numerical device simulation results for extremely scaled Leff=25 nm double-gate devices and bulk-Si device.