Synthesis of arrays and records

Abstract

The use of arrays and records in modern hardware-description languages (HDL) allows designs to be modeled at very high levels of abstraction. However, the support for these complex data types in current synthesis tools is very limited. This paper presents a comprehensive scheme to synthesize aggregate data types such as arrays and records, in a very general manner. The approach consists of mapping objects (variables and signals) of aggregate data types onto one-dimensional vectors, and generating specialized addressing/decoding hardware to be able to access any field of the data type. Arrays of multiple dimensions and any level of nesting of arrays and records are supported. This paper describes the whole process, from the language specification to the actual hardware structures created by synthesis.