Sub-lithographic atomic-build nanowire gate structure for improved FET performance

Abstract

Many nanowire or nanotube FET structures have been reported on over the past years, as possible replacements for conventional logic devices, because of their improved frequency performance [1], [2]. These nano-structures are built using various assembly techniques, some even derived from traditional lithographic methods. Many of these techniques involve the use of scanning tunneling microscopes (STM) to measure the electrical performance of the nanowires or nanotubes as logic or analog devices. However, this paper is a proposal on how such STM techniques can be applied to the construction of sub-lithographic gates on otherwise conventional III-V gate structures, in order to reduce the physical gate length to about 1am. Use of the STM for atomic-level construction was first reported in 1989 at IBM Almaden [3], and this work has continued, delivering advanced molecular cascade logic structures built atom-by-atom [4]. This technology has been demonstrated to be capable of building a nanowire of length about 100nm and width about 1nm [5] -which is ideally suited to the construction of a high-performance III-V FET gate. Projected FT of such a MHEMT (metamorphic high electron mobility transistor: higher Indium doping is used to improve the electron mobility in the channel) based structure is 0.5THz, and follow-on work would be done in conjunction with NIST to measure the performance of such a nanowire gate structure, as precursor to the construction of such a FET. © 2006 EuMA.