David A. Papa, Tao Luo, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion is essential for achieving timing closure. This work studies buffer insertion under two types of constraints: (i) avoiding blockages, and (ii) inserting buffers into pre-determined buffer bay regions. We propose a general Steiner tree routing problem to drive this application and present a maze-routing based heuristic. We show that this approach leads to useful solutions on industry designs.
David A. Papa, Tao Luo, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shiyan Hu, Zhuo Li, et al.
DAC 2009
C.N. Sze, Jiang Hu, et al.
ASP-DAC 2004
Zhuo Li, C.N. Sze, et al.
ASP-DAC 2005