Haoxing Ren, David Z. Pan, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer insertion is essential for achieving timing closure. This work studies buffer insertion under two types of constraints: (i) avoiding blockages, and (ii) inserting buffers into pre-determined buffer bay regions. We propose a general Steiner tree routing problem to drive this application and present a maze-routing based heuristic. We show that this approach leads to useful solutions on industry designs.
Haoxing Ren, David Z. Pan, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bing Lu, Jiang Hu, et al.
ISPD 2003
Charles J. Alpert, Anirudh Devgan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
C.N. Sze, Charles J. Alpert, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems