Conference paper
Process variation aware clock tree routing
Bing Lu, Jiang Hu, et al.
ISPD 2003
Buffer insertion is essential for achieving timing closure. This work studies buffer insertion under two types of constraints: (i) avoiding blockages, and (ii) inserting buffers into pre-determined buffer bay regions. We propose a general Steiner tree routing problem to drive this application and present a maze-routing based heuristic. We show that this approach leads to useful solutions on industry designs.
Bing Lu, Jiang Hu, et al.
ISPD 2003
Zhuo Li, C.N. Sze, et al.
ASP-DAC 2005
Zhanyuan Jiang, Shiyan Hu, et al.
ICCAD 2006
Yaoguang Wei, Cliff Sze, et al.
ACM TODAES