Magnetoresistive random-access memory (MRAM) technology and recent developments in fabrication processes have shown it to be compatible with Si-based complementary metal oxide semiconductor (CMOS) technologies. The perpendicular spin transfer torque MRAM (STT-MRAM) configuration opened up opportunities for an ultra-dense MRAM evolution and was most widely adapted for its scalability. Insertion of STT-MRAM in the back end of line (BEOL) wiring levels has many advantages, including density, latency, and endurance with the promise of being comparable to performance of dynamic random access memory technology (DRAM). There are several important parameters at multiple process steps which require precise metrology for STT-MRAM integration. Inline metrology of the magnetic tunnel junction (MTJ) pillar is vital to calibrate the magnetic read/write performance parameters. This work discusses various challenges to monitor critical process steps for integrating STT-MRAM in advanced CMOS technologies and key metrology solutions are presented. To precisely predict MRAM junction resistance early in the process flow, a machine learning model was developed using scatterometry spectra collected after MTJ pillar formation and corresponding resistance data from the end of line electrical test. This machine learning model utilizes metrology data from the pillar formation process and can predict accurate device resistance values. Additionally, carefully monitoring the required planarization process of an interlayer dielectric deposited after the MTJ pillar formation is critical to avoid subsequent defects. Several modelling techniques are discussed and a new spectral interferometry-based technique, vertical travelling scatterometry (VTS), is demonstrated as a solution for measurements on fully integrated device areas.