The performance and reliability of submicron polysilicon TFTs (thin-film transistors) depend largely on the gate insulator and the interface between the active polysilicon layer and the gate insulator. Submicron TFTs with 10-nm gate oxides using both conventional thermal oxides and PECVD (plasma enhanced chemical vapor deposited) oxides have been fabricated starting with various treated polysilicon and amorphous silicon (a-Si) active layers. A model based on quantum-mechanical tunneling of carriers from polysilicon asperities into the poly-oxide as a function of the electric field at the injector, as determined by the radius of the asperities, is applied to the data. The results of the model are consistent with the data. Lattice imaging electron microscopy (TEM), ellipsometry, and electrical capacitance have been implemented to determine poly-Si TFT parameters. Constant-current-stress and dark-ramp I-V techniques have been used to electrically characterize the submicron poly-Si TFTs.