A major limitation in high-power three-dimensional chip stacks is the heat removal of dissipated power. To this end, highly thermally conductive intra-stack bondlines are required. Percolating thermal underfills (PTUs), where densely packed micron-sized dielectric particles fill the open space resulting from the electrical interconnects between individual chips, are expected to improve the effective thermal conductivity within the chip stack. Even more so, the thermal performance of the layer is additionally enhanced by areal contacts between micron-sized features created by the self-Assembly of nanoparticles. Accurate and precise thermal characterization of these underfill layers is required for appropriate electronic packaging design. In this paper, a technique is introduced to allow the thermal characterization on non-dense thin material layers, such as particles only. The effects of different material combinations are investigated, as well as processing influences. Ultimately the effects of dielectric nanoparticle neck contributions are determined, showing a 2.4-fold thermal conductivity increase for an appropriate mixture of large and small nanoparticles, compared to microparticles only. This constitutes a very significant improvement to state-of-The-Art thermal underfill systems, which will enable more efficient electronic packaging designs and ultimately contribute to energy savings.