PERFORMANCE-ORIENTED SYNTHESIS IN THE YORKTOWN SILICON COMPILER.

Abstract

Some algorithms are presented for optimization of the switching-time performances of synchronous systems designed by the Yorktown silicon compiler. Circuit performance is related to the worst-case propagation delay of signals between two register boundaries, and the optimization of circuit performance is equivalent to the minimization of the critical path delay through combinational circuits. The author considers a global approach to timing performance optimization which involves operations at the logic, topological and physical level of description of the circuit. In particular, at the logic level, he modifies the internal structure of the logic gates and their interconnection inside each combinational module. At the topological level, he repositions the modules, and as a consequence their gates, to reduce the delay on the wires along the critical paths. At the physical design level, the author optimizes the gate sizes to improve the switching speed. These operations are interlaced with the synthesis steps of the Yorktown silicon compiler and can be seen as the 'code optimizer' part of the compiler that may be invoked when compiling circuits with critical timing performance.