Performance and design choices of level-two caches

Abstract

The increasing disparity of speed between processor and its main memory makes ways for multi-level cache hierarchies in almost any of today's computer systems; specifically, the second-level (L2) caches with larger capacity but longer access time than the first-level (L1) caches have been adopted to reduce this memory gap. In this study an enhanced one-pass trace-driven simulation technique is used to evaluate the design choices of three L2 cache parameters: associativity, line size, and cache size. The traces are from large workloads of both commercial and scientific applications. Quite the contrary to other studies, we found that fast L2 access time can be more important than a larger size or associativity. Thus, trade-offs of L2 cache parameters are essentially the same as those of the L1 caches despite the fact that their reference patterns and miss ratios are very different. Moreover, since large L2 caches generally require larger line sizes, line utilization has a direct impact on memory traffic and varies significantly from application to application. Our data indicate that a simple sectoring technique with smaller traffic units can substantially reduce the memory traffic.