Optimal CMOS cell transistor placement: A relaxation approach

Abstract

A relaxation approach for producing a placement of transistors in a CMOS cell in a grid layout style from the circuit schematic diagram is described. For a given objective function, the approach leads to optimal results in most of the cases attempted. Unlike previous constructive approaches, this approach is iterative. It is also quite flexible. It can be used for unrestricted circuit types and can handle a variety of other important parameters affecting the wirability of layout. The procedure is targeted for use in the automatic generation of custom and gate-array cell libraries.