On the Write Schemes and Efficiency of FeFET 1T NOR Array for Embedded Nonvolatile Memory and Beyond

Abstract

Ferroelectric field-effect-transistor (FeFET) 1T NOR Array is promising for multiple applications yet not well studied on its write mechanism and schemes. In this work, we demonstrate: i) A comprehensive model which reflects two FeFET write mechanisms - one to ground Source (S), Drain (D) & Body (B) nodes and use Gate (G) to write, and the other to float S/D and use G & B to write; ii) 3 write schemes for conventional FeFET 1T NOR arrays and another one for the diagonal array, the latter of which shows the advantages of low write energy and high write efficiency but with the penalty area cost; iii) A study of parasitic parameters, particularly gate resistance (Rg), gate capacitance (Cg) and word line resistance (RWL), in FeFET 1T NOR array, which is critical for further prospective 1T NOR array design; iv) An implementation of FeFET 1T NOR array in the Ising machine system to evaluate the feasibility of our write scheme and array structure for embedded nonvolatile memory (NVM) applications.