Publication
S3S 2015
Conference paper

Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance

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Abstract

This paper analyses the impact of 10nm Si cap layer for UTBB pFET eSiGe, with 35% Ge in channel and source/drain. For the first time, it is found that this Si cap can improve both access resistance and hole mobility in narrow structures.

Date

20 Nov 2015

Publication

S3S 2015

Authors

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