Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
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7 results for C. Waskiewicz
An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging
- Joel A. Bahena
- Phillip Tyler
- et al.
- 2023
- Advancing Microelectronics
Reliable Cu Pillar Undercut Control Using the Endpoint Detection System
- Zachary Gardner
- Soon-Cheon Seo
- et al.
- 2024
- ASMC 2024
Manufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning
- Susan Fan
- P. Jamison
- et al.
- 2023
- ASMC 2023
56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via
- James Hsueh-Chung Chen
- Christopher Waskiewicz
- et al.
- 2012
- IITC 2012
Spacer-defined double patterning for 20-nm and beyond logic BEOL technology
- Ryoung-Han Kim
- Chiew-Seng Koay
- et al.
- 2011
- SPIE Advanced Lithography 2011
BEOL Cu CMP process evaluation for advanced technology nodes
- Kunaljeet Tanwar
- Donald Canaperi
- et al.
- 2013
- JES