Lithography and fabrication processes for sub-100 nm scale complementary metal-oxide semiconductor

Abstract

The fabrication of integrated complementary metal-oxide-semiconductor devices and circuits that scale into the sub-100nm regime is presented. While the devices are essentially conventional in design, significant innovations have been required to build them. These innovations combine new materials, lithography, etching, and processing technologies. Moreover, theoretical models of novel devices, such as the double gate transistor, suggest that metal-oxide-semiconductor field-effect transistors may be scaled down to gate lengths of 30nm.