Hiroyoshi Kawasaki, Brett M. Clark, et al.
IEEE TNS
Paper
Latch design techniques for mitigating single event upsets in 65 nm SOI device technology
Abstract
This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments. © 2007 IEEE.
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